1. Field of Invention
The present invention generally relates to the charge pump circuit and cell thereof, and more particularly to the charge pump circuit and cell thereof with faster start-up time.
2. Description of Prior Art
The semiconductor memories need a high voltage for writing data. However, the supply voltage is usually low, and thus a charge pump circuit is needed in the semiconductor memories.
Referring to FIGS. 1 and 2, FIG. 1 is a circuit diagram of a conventional charge pump circuit 10, and FIG. 2 is a waveform diagram of the clock signals in the charge pump circuit 10. The charge pump circuit 10 is a Dickson charge pump circuit. The charge pump circuit 10 comprises a plurality diodes D(1)˜D(N+1) which are connected in series, a plurality of capacitors C(1)˜C(N), Cout and inverters I(1)˜I(N). The inverter I(k) is used to receive the clock signals CLK1 or CLK2, where k is a positive integer less than N+1. When k is even, the inverter I(k) is used to receive the clock signal CLK2; and when k is odd, the inverter I(k) is used to receive the clock signal CLK1. The output of the inverter I(k) is coupled to one end the capacitor C(k), and another end of the capacitor C(k) is coupled to the output of the diode D(k). The capacitor Cout is coupled to the output of the diode D(N+1).
Each two diodes, capacitors and inverters can be considered as a charge pump cell, such as the charge pump cell 101. The charge pump cell is used to pump the input voltage of the charge pump cell 101, and thus the output voltage increases. As shown in FIG. 1, the output voltage of the charge pump circuit is about (N+1)*Vcc. The capacitors C(1)˜C(N) and Cout have the size limitations in the practical implementation, and thus the performance of the charge pump circuit 10 may be poor.
Referring to FIGS. 3 and 4, FIG. 3 is a circuit diagram of another conventional charge pump circuit 30, and FIG. 4 is a waveform diagram of the clock signals in the charge pump circuit 30. The charge pump circuit 30 is disclosed in the article of Lauterbach et al., “Charge Sharing Concept and New Clocking Scheme for Power Efficiency and Electromagnetic Emission Improvement of Boosted Charge Pumps” pressed by IEEE in May, 2005. The charge pump circuit 30 comprises a plurality of transistors M1˜M4, T1˜T5 and a plurality of capacitors C1˜C8. The connections among the transistors M1˜M4, T1˜T5 and the capacitors C1˜C8 are shown in FIG. 3, and are not described herein again.
The charge pump circuit 30 has the better power efficiency than that of the Dickson charge pump circuit. Furthermore, the charge pump circuit 30 improves the electromagnetic emission. However, the start-up time of the charge pump circuit 30 is not improved, and thus it is not suitable for the high speed operation system.
Referring to FIGS. 5 and 6, FIG. 5 is a circuit diagram of another conventional charge pump circuit 50, and FIG. 6 is a waveform diagram of the clock signals in the charge pump circuit 50. The charge pump circuit 50 is disclosed in U.S. Pat. No. 7,030,683. The charge pump circuit 50 comprises a plurality of transistors TR, T1, T2, diodes Td, a plurality of pre-charge diodes DPC, and a plurality of capacitors C0˜C2. The connections among the transistors TR, T1, T2, the diodes Td, the pre-charge diodes DPC, and the capacitors C0˜C2 are shown in FIG. 5, and are not described herein again.
In the Dickson charge pump in which the serially connected diodes sequentially respond to anti-phase 50/50 clock cross over or overlapped (CLK1, CLK2). However efficiency of the charge pump circuit 50 is increased by providing with each diode a charge transfer transistor T1 in parallel therewith between two adjacent nodes V1, V2, and driving the charge transfer transistor T1 to conduction during a time when the parallel diode Td is conducting thereby transferring any residual trapped charge at one node V1 through the charge transfer transistors T1 to the next node V2. Operating frequency can be increased by providing a pre-charge diode DPC coupling an input node to the gate of the charge transfer transistor T1 to facilitate conductance of the charge transfer transistor, and by coupling the control terminal of the charge transfer transistor T1 to an input node V1 in response to charge on an output node V2 to thereby equalize charge on the control terminal and on the input node V1 during a recovery period.
Although the charge pump circuit 50 has a good power efficiency, the charge pump circuit 50 needs the critical timing control of the clock signals phi1˜phi4 (as shown in FIG. 6). However, the critical timing control increases the complexity of the charge pump circuit 50, and thus the charge pump circuit 50 may not operate at high speed.
Referring to FIGS. 7 and 8, FIG. 7 is a circuit diagram of another conventional charge pump circuit 70, and FIG. 8 is a waveform diagram of the clock signals in the charge pump circuit 70. The charge pump circuit 70 is disclosed in U.S. Pat. No. 6,642,773. The charge pump circuit 70 is used for generating high positive voltages. The charge pump circuit 70 has an input unit 101, a plurality of driving units 102, and an output unit 103. The charge pump circuit 70 has n-channel metal-oxide semiconductor (NMOS) transistors. Each of the driving units 102 has a plurality of capacitors 104, 106 and a plurality of transistors 108, 110, 112. A clock generator 114 is used for generating a first clock signal 115, a second clock signal 116, a third clock signal 117, and a fourth clock signal 118 inputted into the driving units 102. The connections among all of the elements of the charge pump circuit 70 are shown in FIG. 7, and are not described herein again.
If the charge pump circuit 70 has more driving units 102 cascaded in series, the charge pump circuit 70 can output a higher positive voltage. The voltage level of node Y varies according to the voltage level of node Z when the transistor 112 is turned on. Therefore the body effect is greatly cut down without reducing the actual output voltage and the efficiency of raising voltage levels is greatly improved. In addition, when one driving unit is operating, other adjacent driving units will not operate to interfere with the driving unit that is working. Although the charge pump circuit 70 has reduced the body effect and improved the efficiency, the driving capability and the start-up time have not been improved.
In order to solve these and other problems as stated above, the embodiment of the invention provides a charge pump circuit and cell thereof with fast start-up time and high driving capability.